Paper Review: An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization

Abstract
A general sequential circuit consists of a number of combinational stages that lie between latches. For the circuit to meet a given clocking specification, it is necessary for each combinational stage to satisfy a certain delay requirement. Roughly speaking, increasing the sizes of some transistors in a stage reduces the delay, with the penalty of increased area. The problem of transistor sizing is to minimize the area of a combinational stage, subject to its delay being less than a given specification. Although this problem has been recognized as a convex programming problem, most existing approaches do not take full advantage of this fact, and often give nonoptimal results. An efficient convex optimziation algorithm has been used here. This algorithm is guaranteed to find the exact solution to the convex programming problem. We have also improved upon existing methods for computing the circuit delay as an Elmore time constant, to achieve higher accuracy. CMOS circuit examples, including a combinational circuit with 832 transistors are presented to demonstrate the efficacy of the new algorithm.

Paper Location
IEEEXplore

Citation
[1] S. Sapatnekar, V. Rao, and P. Vaidya, "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, 1993, pp. 1621-1634.

Positive

• Very cool idea, adapting the properties of the problem to meet a specific criteria and effectively moving the problem to another "space" to find a more efficient solution.
• Good use of experimental verification of some approximations, such as the internal capacitances of the transistor as they increase.
• Use of examples to illustrate how certain parts of the methodology work!
  

Negative

•   The paper does not present a full solution, and in fact completely ignores the hold times of the following stage.
• Makes the assumption that the rising and falling edges of the output of a component are 2(delta)h and 2(delta)l, not necessarily a reasonable assumption
• Assumes the rise time of a gate is strictly limited by n-type transistors. Could be limited by PMOS, quite reasonably.
• Claims the development of a heuristic that is exact for series-parallel graphs - but it's not a heuristic if it is exact! Poor wording.
• Uses an equation for Alpha that has no readily apparent origin.
• Poor definition of their experimental setup. "The technology parameters here correspong to a submicron technology." Which submicron technology?
• Fails to provide good comparison against other solutions to this problem in terms of runtime and ability to solve the solution.