Paper Review: Clock Skew Optimization

Abstract

This paper investigates the problem of improving the per- formance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops. Through the use of a model to detect clocking hazards, two linear pro- grams are investigated: 1) Minimize the clock period, while avoiding clock hazards. 2) For a given period, maximize the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS.

Paper Location
None

Citation
[1] J.P. Fishburn, "Clock Skew Optimization," Theory and Practice, vol. 39, 1990, pp. 945-951.
Positive

• Good, concise description of a variety of different clock hazards.
• Provides directions for future research, typically a sign of a large body of work to yet be done.

Negative

• Number of benchmarks this is run on is not really good enough to give an idea of this algorithm's ability.
• This is really more of a sketch of how to do soemthing, than actually any of the real implementation
• Fails to consider jitter anywhere along the way, particularly in its final graphs.