Status Goals and Plans For Jan 04, 2010

Main Goal:  Spend winter break reading literature and find both an area and a niche to fill.

Accomplished

• Read many papers
• Generated a Research Ideas list
• Found areas of interest

Longer Term Goals

• Complete DoE Fellowship Application
• Investigate DHS Fellowship & NASA GSRP
• Assist Kal in getting started
• Electrical Engineering Labs Book
  

Short Term Planned

• Keep reading
• Think of 223 projects

Read
[1] D. Blaauw, K. Chopra, A. Srivastava, and L. Scheffer, "Statistical Timing Analysis: From Basic Principles to State of the Art," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, 2008, pp. 589-607.
[2] M. Guthaus, N. Venkateswarant, C. Visweswariaht, and V. Zolotov, "Gate sizing using incremental parameterized statistical timing analysis," Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, IEEE Computer Society, 2005, p. 1036.
[3] A.B. Kahng, "Classical floorplanning harmful?," Proceedings of the 2000 international symposium on Physical design - ISPD '00, 2000, pp. 207-213.
[4] H. Murata, K. Fujiyoshi, and M. Kaneko, "VLSI/PCB placement with obstacles based on sequence-pair," Proceedings of the 1997 international symposium on Physical design, ACM New York, NY, USA, 1997, p. 26–31.
[5] Y. Chang, Y. Chang, G. Wu, and S. Wu, "B•-Trees: a new representation for non-slicing floorplans," Proceedings of the 37th conference on Design automation, ACM New York, NY, USA, 2000, p. 458–463.
[6] S. Adya and I. Markov, "Fixed-outline floorplanning through better local search," Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001, 2001, pp. 328-334.
[7] S. Sapatnekar, V. Rao, and P. Vaidya, "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, 1993, pp. 1621-1634.
[8] L. Van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," Proc. IEEE Int. Symp. on Circuits and Systems, 1990, p. 865–868.
[9] J. Hu, C. Alpert, S. Quay, and G. Gandham, "Buffer insertion with adaptive blockage avoidance," Proceedings of the 2002 international symposium on Physical design, ACM, 2002, p. 97.
[10] T. Chao, Y. Hsu, J. Ho, K. Boese, and A. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems, vol. 39, 1992, p. 799–814.
[11] R. Tsay, "An exact zero-skew clock routing algorithm," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, 1993, pp. 242-249.
[12] P. Groeneveld, N. Shenoy, and D.A. Conference, "How to review a DAC Paper," Program, 2009.
[13] S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda, and D. Blaauw, "Duet: An Accurate Leakage Estimation and Optimization Tool for Dual-Vt Circuits," IEEE Transactions on Very Large Scale Integration, vol. 10, 2002, pp. 79-90.