Paper Review: Zero skew clock routing with minimum wirelength

Abstract
In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper we first present the deferred-merge embedding (DME) algorithm, which embeds any given connection topology to create a clock tree with zero skew while minimizing total wirelength. The algorithm always yields exact zero skew trees with respect to the appropriate delay model. Experimental results show an 8% to 15% wirelength reduction over previous constructions in [17] and [18]. The DME algorithm may be applied to either the Elmore or linear delay modela, and yields optimal total wirelength for linear delay. DME is a very fast algorithm, running in time linear in the number of synchronizing elements. We also present a unified BB + DME algorithm, which constructs a clock tree toplogy using a top-down balanced bipartition (BB) approach, and then applies DME to that topology. Our experimental results indicate that both the toplogy generation and embedding components of our methodology are necessary for effective clock tree construction. The BB+DME method averages 15% wirelength savings over the previous method of [17], and also gives 10% average wirelength savings when comapred to the method of [25]. The paper concludes with a number of extensinos and directions for future research.

Paper Location
Google Scholar

Citation
[1] T. Chao, Y. Hsu, J. Ho, K. Boese, and A. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. on Circuits and Systems, vol. 39, 1992, p. 799–814.
Positive

• The introductory discussion provides a very strong literature survey of all the other related papers, and where this one fits in
• Good verification against the SPICE models and shows that the approximations are valid.
• The algorithm presented runs in linear time, this is a very good feature of this paper.
• Good data comparsion and presentation.
• Paper includes ideas for future work! Very good!

Negative

• Sink as a term for a synchronizing element is confusing terminology, when in the same type of design methodology, a sink can also mean ground.
• Uses three representations for placement in a single paper, the author should really have cleaned this up.
• Considers only delay on a single plane (R^2) and does not consider several layers (R^3)
• Integration with Elmore delay is often very good, but there are cases where it is extremely poor, despite being the more accurate model used.