Paper Review: An exact zero-skew clock routing algorithm

Abstract
In this paper we present an exact zero-skew clock routing algorithm using the Elmore delay model. The results have been verified with accurate waveform simulation. We first review a linear time delay computaiton method. A recursive bottom-up algorithm is then proposed for interconnecting two zero-skewed subtrees to a new tree with zero skew. The algorithm can be applied to single-staged clokc trees, multistaged clock trees and multi-chip system clock trees. The approach is ideal for hierarchical methods of constructing large systems. All subsystems can be constructed in parallel and independently, then interconnected with exact zero skew. Extensions to the routing of optimum nonzero-skew clock trees (for cycle stealing) and multiphased clock trees are also discussed.

Paper Location
IEEE Xplore

Citation
[1] R. Tsay, "An exact zero-skew clock routing algorithm," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, 1993, pp. 242-249.

Positive

• The presentation shows a novel rethink of the priorities of the problem, namely swtiching form focusing on wire length balancing to the slightly more abstract clock delay balancing.
• Strong use of theta notation to denote runtime, and not simply upper bound. This type of notation seems to be missing from more modern papers.
• Very strong use of different model types and justification for their uses in simplification where appropriate.

Negative

• Does not take into consideration clock jitter specifically, though on some level it can be lumped in with the paper's P0 constant, despite being very arbitrary and simply there to fit data.
• While the focus is on clock tree balancing, the routing area is not considered and meander lines are necessary to achieve the end goal.