Updates for 01/11/10

Main Goal:
Build on clock router to add in effects of stub-tuning, rounded
corners and made purely planar

Accomplished:

•  Seg faulted current VLSIDA clock router under Ubuntu. (After many build issues)
• Read deeply on current clock routing techniques
• Stumbled upon the 280G paper I would like to review
• Got clock routing code running on Quiche

Goals:

• Understand characteristic impedance of single-ended lines better
• Understand stub tuning of single-ended lines better
• Simulate the spectral components of a 10ps rise time
• Simulate loss due to 90 degree corners
• Modify clock code to use impedance instead of purely RC components
• Modify clock code to consider rounded corners by way of no OPC
• Look into geometry of corners when OPC is turned off.

Read:
[1] E. Friedman, "An RLC interconnect model based on fourier
analysis," IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. 24, 2005, pp. 170-183.
[2] Z. Jiang, S. Hu, J. Hu, Z. Li, and W. Shi, "A new RLC buffer
insertion algorithm," Proceedings of the 2006 IEEE/ACM international
conference on Computer-aided design, ACM, 2006, p. 557.
[3] B. Taskin, J. Demaio, O. Farell, M. Hazeltine, and R. Ketner,
"Custom topology rotary clock router with tree subnetworks," ACM
Transactions on Design Automation of Electronic Systems, vol. 14,
2009, pp. 1-14.
[4] F. O'Mahony, C.P. Yue, M.a. Horowitz, and S.S. Wong, "Design of a
10GHz clock distribution network using coupled standing-wave
oscillators," Proceedings of the 40th conference on Design automation
- DAC '03, 2003, p. 682.
[5] M. El-Moursy and E. Friedman, "Exponentially tapered H-tree clock
distribution networks," IEEE Transactions on Very Large Scale
Integration(VLSI) Systems, vol. 13, 2005, p. 971–975.
[6] J. Wood, T. Edwards, and S. Lipa, "Rotary traveling-wave
oscillator arrays: a new clock technology," IEEE Journal of
Solid-State Circuits, vol. 36, 2001, pp. 1654-1665.

223:
[1] J. Cong, "Minimum-cost bounded-skew clock routing," Proceedings of
ISCAS'95 - International Symposium on Circuits and Systems, vol. 2775,
pp. 215-218.
[2] J.P. Fishburn, "Clock Skew Optimization," Theory and Practice,
vol. 39, 1990, pp. 945-951.
[3] a. Farrahi, a. Srivastava, G. Tellez, and M. Sarrafzadeh,
"Activity-driven clock design," IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 20, 2001, pp. 705-714.