We present a fast and efficient combinatorial algorithm to simul- taneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the high redundancy, a mesh architecture offers high tolerance towards variation in the clock skew. However, such a redundancy comes at the expense of mesh wire length and power dissipation. Based on survivable net- work theory, we formulate the problem to reduce the clock mesh by retaining only those edges that are critical to maintain redun- dancy. Such a formulation offers designer the option to trade-off between power and tolerance to process variations. Experimental results indicate that our techniques can result in power savings up to 28% with less than 4% delay penalty.
Paper Location
ACM Portal
Citation
[1] G. Venkataraman, Z. Feng, J. Hu, and P. Li, "Combinatorial algorithms for fast clock mesh optimization," Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, ACM, 2006, p. 567.
Positive
- Extremely fast runtime of the algorithm.
- New model for gate delay with fast runtime, particularly compared to HSpice
- Great adaptation of a problem from another field (networks)
Negative
- Discusses several possible algorithms to solve steiner optimization but dismisses them with little validation
- Fails to present validation of their driver against spice models (in terms of voltage graphs)
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