Updates for 01/18/10

Main Goal:
Build on clock router to add in effects of stub-tuning, rounded
corners and made purely planar

Accomplished:

• Understand that single-ended lines do not have a simple impedance, ground return always plays a key role.
• Read through and found the knee frequency of a 10ps rise time.
• Found the geometry of corners with OPC off may be relatively close to the desired corners for large power transfer. Also discovered that on the large metal wires, the feature size is large enough that OPC may not need to be done in the first place.
• Wrote a 1-page summary for Matt to edit for SRC
• Toyed around with Spice and Matlab picking up certain bits of the command line ngspice
• Spent a ridiculous amount of time trying to reproduce the first graph in RLC interconnect, and failing. Off by several orders of magnitude.

Goals:

• Modify clock code to use a planar DME algorithm
• Modify clock code to consider rounded corners
• Figure out why the graph is wrong
• Add in third harmonic from model in RLC Interconnect to have accuracy above 9GHz (Need the graph to get a good estimate of frequency accuracy limit)

Read:
223:
[1] G. Venkataraman, Z. Feng, J. Hu, and P. Li, "Combinatorial
algorithms for fast clock mesh optimization," Proceedings of the 2006
IEEE/ACM international conference on Computer-aided design, ACM, 2006,
p. 567.

280G:
[1] Z. Feng, Y. Hu, L. He, and R. Majumdar, "IPR: In-Place
Reconfiguration for FPGA Fault Tolerance," ICCAD, ICCAD, 2009, pp.
1-4.

EE270:
[1] D. Panescu, "Emerging technologies. Implantable neurostimulation
devices.," IEEE engineering in medicine and biology magazine: the
quarterly magazine of the Engineering in Medicine \& Biology Society,
vol. 27, 2009, p. 100.
[2] B.S. Wilson and M.F. Dorman, "The surprising performance of
present-day cochlear implants.," IEEE transactions on bio-medical
engineering, vol. 54, 2007, pp. 969-72.